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| r07ds0892ej0100 rev.1.00 page 1 of 23 aug 02, 2013 data s heet raa207703gbm/7704gbm/7705gbm synchronous buck regulator with internal power mosfets description the raa20770 3 gbm is monolithic synchronous buck regulator with power mosfets in extremely small package. the raa20770 3 gbm delivers high output current by sm all rds(on) power mosfets. constant on time control architecture provides fast transient response, and minimize external components. the raa20770 3 gbm operates skip mode at light load, it provides high efficiency in all load condition. the raa207703gbm inco rporates internal 5v ldo, so the regulator can operates single power supply. three current ability products can be selected. features i nput voltage range: 5.5 v to 16 v (internal ldo use), 3.0 v to 16 v (external 5 v use) out put voltage range: 0.8 v to 5.0 v constant - on - time control built - in power mosfets suitable for pc, server application internal 5 v ldo for single power supply operation 5 v ldo / external 5 v input selectable (ldo remote on/off) switching frequency: adjustable up to 2 mhz high average o utput current, up to 15 a (770 3 gbm), 10 a (770 4 gbm), 5 a (770 5 gbm) controllable driver: remote on/off power good function over current protection / over voltage protection / thermal shutdown function built - in bootstrapping diode soft start period adjustable en hanced l ight l oad mode function for higher efficiency extremely small chip size package with solder bump pb - free/halogen - free application circuit v5_out on/off pgood sgnd avin vin sw pgnd boot vin raa207703gbm raa207704gbm raa207705gbm ss ldo_en# vout set fb r07ds0892ej0100 rev.1.00 aug 02, 2013
raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 2 of 23 aug 02, 2013 pin arrangement top view sw sw sw sw sw boot vin vin vin sgnd set sw pgo od avin sw sw sw sw ss on/ off fb vin vin ldo_ en# v5_ out avin ldo_ en# v5_ out avin ldo_ en# v5_ out avin ldo_ en# v5_ out avin ldo_ en# v5_ out avin ldo_ en# v5_ out boot sgnd set pgo od ss on/ off fb boot sgnd set pgo od ss on/ off fb a a a 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 g f e d c b f e d c b d c b pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd sw sw sw sw vin vin vin sw sw sw sw sw sw sw sw sw vin vin vin vin vin pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 3 of 23 aug 02, 2013 pin description pin name pin no. description remarks v 5_out 1a controller voltage controller supply (5 v regulator output) sgnd 2a controller analog gnd should be connected to pgnd on pcb pattern fb 3a feedback voltage in put pin l do _ en# 4a internal 5 v ldo enable pin av in 5a analog input voltage should be connected to vin on pcb pattern boot 1b bootstrap voltage pin to be supplied +5 v through integrated sbd set 2b constant on time program pin tie resistor between sw and set pin pgood 3b power good indicator pin pull low when no good (open drain output) ss 4b soft start period program pin tie capacitor between ss and sgnd on/off 5b operation enable pin operation stop when " l " signal asserted vin ? input voltage sw ? switching node pgnd ? power gnd should be connected to sgnd on pcb pattern note: pin assign of 1a - 5a & 1b - 5b is common through raa20770 3 gbm, raa20770 4 gbm and raa20770 5 gbm. raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 4 of 23 aug 02, 2013 block diagram control logic enable tsd uvlo boot on/off 1m enable 1m tsd tsd uvlo uvlo 4.3 v ovp 0.8 v 1.0 v 2.5 ma fault fault enable uvlo ripple comparator + ? + ? + 0.72 v ? + 1 shot timer delay ovp ocp tsd fault protection function sw pgnd v5_out zcd comparator zcd ovp ? + ocp ocp v5_out vin avin set sgnd fb pgood ss ldo_en# 5v ldo 1 . truth table for the on/off pin 2. truth table for l do_en# pin on/off input driver chip status l do_en# input 5 v regulator status "l" shutdown (operation stop) "l" ldo enable "open" shutdown (operation stop) "open" ldo enable "h" enable (normal op eration) "h" ldo dis able raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 5 of 23 aug 02, 2013 absolute maximum ratings (ta = 25 c) item symbol ratings unit notes input voltage vin , avin ? 0.3 to + 20 v 1 switch node voltage sw 20(dc), 23(<10 ns) v 1 boot voltage vboot 25(dc), 28(<10 ns) v 1, 2 controller voltage v 5_ou t ? 0.3 to + 6 v 1 v5_out current icc ? 20 to +0.1 ma 3 fb pin voltage v fb ? 0.3 to v 5_out +0.3 v 1, 4 on/off voltage v on/off ? 0.3 to vin v 1 ldo_en# voltage v ldo_en# ? 0.3 to vin v 1 set voltage v set ? 0.3 to vin v 1 pgood voltage v pgood ? 0.3 to vin v 1 pgood sink current i pgood +2 ma 3 operating junction temperature tj - opr ? 40 to +125 c storage temperature tstg ? 55 to +150 c notes: 1. rated voltages are relative to voltages on the sgnd and pgnd pins. 2. boot ? v 5_out < 20 v 3. for rated current, ( +) indicates inflow to the chip and ( ? ) indicates out flow . 4. v 5_out + 0.3 v < 6 v thermal information item symbol part no. value unit note thermal resistance (junction to air when device is mounted on evaluation board) q j - a raa207703gbm 27 c/w 1 raa207704gbm 33 raa207705gbm 39 note: 1. not assured value, just reference for design. above data is taken using renesas's reference board. recommended operating condition item symbol ratings unit remarks input v oltage vin 3.0 to 16 v analog i nput v oltage avin 4.5 to 16 v controller voltage v5_out 4.5 to 5.5 v when v5_out is supplied externally continuous output current iout 0 to 15 0 to 10 0 to 5 a 15 a: raa207703gbm 10 a: raa207704gbm 5 a: raa207705gbm raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 6 of 23 aug 02, 2013 electrical characteristics ( ta = 25 c, vin = 12 v, unless otherwise specified ) item symbol min typ max unit test conditions supply a vin start threshold vh ? 4.3 4. 5 v a vin shutdown threshold in ccm vl 3.6 3.8 ? v a vin shutdown threshold in ell mode v l d cm ? 3.0 3.6 v in ell mode (dc m, f sw < 100 khz) a vin quiescent current iq ? 400 5 5 0 m a output = no load, ell mode a vin disable current ( ldo_en# = 12 v ) i i ai n - disbl 1 ? 70 150 m a on/off = 0 v, ldo_en# = 12 v vin disable current ( ldo_en# = 0 v ) i i ai n - disbl 2 ? 130 200 m a on/off = 0 v , ldo_en# = 0 v avin operating current (raa20770 3 gbm) i ci n ? 40 ? ma f sw = 1 m hz , ton = 200 ns avin operating current (raa20770 4 gbm) i ci n ? 35 ? ma avin operating current (raa20770 5 gbm) i ci n ? 20 ? ma vin disable current i i i n - disbl 1 ? ? 5 m a on/o ff = 0 v remote on/off disable level v disbl ? ? 0.6 v 3.3 / 5.0 v interface enable level v enbl 2.0 ? ? v pull - down resistance r disbl 0.7 1 1.3 m w on/off = 1 v 5 v ldo enable 5 v ldo o n level v l do _o n ? ? 0.6 v 5 v ldo o ff level v l do _o ff 2.0 ? ? v pull - down resistance r l do 0.7 1 1.3 m w ldo_en# = 1 v 5 v ldo output 5 v ldo output voltage v l do 4.5 5.0 5.5 v a t no load fb comparator threshold voltage v fb_comp 792 800 808 mv fb input current i fb_in ? 0.1 0 +0.1 m a fb = 1 v 1shot timer high mos fe t on pulse width p w 170 210 250 ns vin = 12 v, rset = 30 k w high mos fet minimum on pulse width p min_on ? 70 ? ns high mos fet minimum off pulse p min_off ? 50 ? ns power good indicator rising threshold on fb v pg_rise 0.67 0.72 0.77 v power good fal ling hysteresis dv pg ? 50 ? mv power good resistance r pg 0.25 0.5 1 k w fb = 0 v soft start soft s tart bias current i ss 1.8 2.5 3. 3 m a over voltage protection ovp trip voltage on fb v ovp 0.95 1.00 1.05 v over current protection ocp trip current (raa 207703 gbm) i ocp 16.0 20.0 24.0 a fixed internally , inductor peak current * 1 ocp trip current (raa20770 4 gbm) i ocp 1 1.5 1 4 .0 1 7 .0 a fixed internally , inductor peak current * 1 ocp trip current (raa20770 5 gbm) i ocp 6.4 8.0 9.6 a fixed internally , inductor p eak current * 1 over temperature protection tsd trip temperature t tsd 130 150 ? c * 1 temperature hysteresis t hys ? 15 ? c * 1 note: * 1 not directly tested. assured by related characteristics test. raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 7 of 23 aug 02, 2013 efficiency performance ( vin = 12 v, l = 1 m h, fsw = 5 00 khz (at ccm) no airflow, unless otherwise specified ) 10 20 30 40 50 60 70 80 90 100 0.001 0.01 1 0.1 efficiency (%) iout (a) 78 80 82 84 86 88 90 92 94 96 98 0 3 6 9 12 15 10 30 20 40 50 60 70 80 90 100 0.001 0.01 1 0.1 efficiency (%) iout (a) iout (a) 0 2 4 6 8 10 iout (a) efficiency (%) 78 80 82 84 86 88 90 92 94 96 98 efficiency (%) 0.001 0.01 1 0.1 efficiency (%) iout (a) 0 1 2 3 4 5 iout (a) raa207703gbm efficiency - output current (light load) raa207704gbm efficiency - output current (light load) raa207703gbm efficiency - output current (heavy load) raa207704gbm efficiency - output current (heavy load) raa207705gbm efficiency - output current (light load) raa207705gbm efficiency - output current (heavy load) 78 80 82 84 86 88 90 92 94 96 98 efficiency (%) 10 30 20 40 50 60 70 80 90 100 vout = 1.0v vout = 1.2v vout = 1.5v vout = 1.8v vout = 3.3v vout = 5.0v vout = 1.0v vout = 1.2v vout = 1.5v vout = 1.8v vout = 5.0v vout = 5.0v vout = 1.0v vout = 1.2v vout = 1.5v vout = 1.8v vout = 3.3v vout = 5.0v vout = 1.0v vout = 1.2v vout = 1.5v vout = 1.8v vout = 3.3v vout = 3.3v vout = 1.0v vout = 5.0v vout = 1.8v vout = 3.3v vout = 1.2v vout = 1.5v vout = 1.0v vout = 1.2v vout = 1.5v vout = 1.8v vout = 3.3v vout = 5.0v raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 8 of 23 aug 02, 2013 operating performance (raa20770 3 gbm, vin = 12 v, vout = 1.2 v, l = 0.42 m h, cout = 5 47 m f, ton = 130 ns , unless otherwise specified ) 1.185 1.190 1.195 1.200 1.205 1.210 1.215 switching frequency - load characteristics fb voltage - temperature characteristics load regulation characteristics line regulation characteristics vout (v) 1.180 1.220 200 400 600 800 1000 fsw (khz) 0 1200 0 4 2 8 6 10 12 14 16 iout (a) 0 4 2 8 6 10 12 14 16 iout (a) 1.185 1.190 1.195 1.200 1.205 1.210 1.215 vout (v) 1.180 1.220 6 8 10 12 14 16 vin (v) 785 790 795 800 805 810 815 fb voltage (v) 780 820 ?50 25 0 ?25 50 75 100 125 temperature (c) vin = 5v iout = 0a iout = 15a iout = 1a vin = 12v vin = 16v raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 9 of 23 aug 02, 2013 operating waveform (raa20770 3 gbm, vin = 12 v, vout = 1.2 v, l = 0.42 m h, cout = 5 47 m f, ton = 130 ns , unless otherwise specified ) typical operation at no load soft-start at no load typical operation at full load soft-start at full load soft-discharge shutdown load transient (0 a to 10 a) 400ns/div. 400ns/div. 400 m s/div. 400 m s/div. 1ms/div. 200 m s/div. il: 5a/div. il: 5a/div. sw: 10v/div. on/off: 5v/div. on/off: 5v/div. pgood: 5v/div. vout: 20mv/div. vout: 1v/div. il: 5a/div. on/off: 5v/div. pgood: 5v/div. vout: 1v/div. il: 5a/div. vout: 50mv/div. il: 5a/div. pgood: 5v/div. vout: 1v/div. sw: 10v/div. vout: 20mv/div. il: 5a/div. raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 10 of 23 aug 02, 2013 desc ription of operation the raa20770 3 gbm operates as voltage - ripple based constant on time control architecture. converter output is controlled by output voltage ripple which is determined by inductor ripple current and esr & esl of output capacitor. each swi tching cycle starts high - side mosfet turn on which time is decided by 1 shot timer. after high - side mosfet turns off, low side turns on, and it keeps until fb voltage becomes lower than reference voltage. in light load condition, low - side mosfet on time is decided by inductor zero current. switching frequency, constant on time setting sw set rset switching frequency in ccm mode is determined by following equation. switching frequency: (vo ut / v in ) ? (1 / ton) [ hz] ? (1) here, ton is high - side mos fet on time, and it is determined by following equation. on time pulse: (5 0 pf ? 1 v / ( v in ? 2.0 v) ) ? rset + 6 0 ns [s] ? (2) from above equation, constant on time is change depend on v in , so switching frequency is almost constant when vin change. this architecture is suitable for battery application. from the above equation, rset is calculated by rset: ( vout / (v in ? fsw) ? 6 0 ns) ? (v in ? 2.0 v) / (50 pf ? 1 v) [ w ] ? (3) here, fsw is switching frequency . 100 200 300 400 500 600 700 800 900 1000 10 30 50 70 90 20 40 60 80 100 rset [k w] on time [ns] on time [ns] 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 4 6 8 10 12 14 16 vin [v] vin = 5 v vin = 8.5 v vin = 12 v rset = 51 k w rset = 30 k w rset = 10 k w minimum on time is 70 ns (typ.), so recommended on time pulse is more than 100 ns. maximum operating frequency is restricted by minimum on time and minimum off time (50 ns, please see next chapter). raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 11 of 23 aug 02, 2013 maximum duty c ycle operation maximum duty cycle is restricted by following equation. max. duty: 1 ? (50 ns ? fsw) ? (4) here, 50 ns means h igh - side minimum off time. if fb voltage does not reach reference voltage after the high - side mosfet turn on time is expired, low - si de mosfet turns on 50 ns, and next switching cycle starts. especially, this condition occurs when output load transient state. sw il (inductor current) 50 ns soft start ss sgnd css soft start ramp period is adjustable by external capacitor (css) selection. when converter start operating, 2 .5 m a current from ss pin charges capacitor between ss and gnd. soft start period is determined by following equation. soft start period: css ? 0.8 v / 2.5 m a [s] ? (5) here, 0.8 v is internal reference voltage vref. ic operates diode emulation mode at soft start period, so it can prevent from reverse current when pre - bias condition. soft start restarts when enable signal re - entered, and after ocp, ovp, ts d, uvl release condition. power good indicator power good indicator is useful for controlling multi - converter systems for sequential start up and shut down. fb voltage is monitored continuously by power good comparator. the power good comparator compares fb pin and 90% internal reference voltage (0.72 v). when fb reaches reference voltage, pgood pin becomes high impedance after internal delay (30% of soft start period). under the fault condition (uvlo, ovp, ocp, tsd), pgood pin is pulled low. 0.72 v 0.80 v soft start period note: pgood pin is connected v5_out through resistor. power good delay (30% soft start period) ss fb vout pgood raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 12 of 23 aug 02, 2013 over voltage protection (ovp) when fb voltage exceeds 125% of reference voltage (1.00 v), switching stops immediately and latched low - side mosfet on state in order to pull the output voltage. to leave the ovp c ondition, v 5_out needs to be pulled under the uvlo level, and re - enter the signal. fb 125% vref high mosfet signal low mosfet signal v5_out pgood note: pgood pin is connected v5_out through resistor. delay over current protection (ocp) ocp detection circuit monitors h igh - side mosfet drain - source current. when the current exceeds fixed level four time s , ic starts hiccup operation. in the hiccup operation, switching stops and operate 1 ms timer. after 1 ms timer is expired, ic operates again from soft start state. if ic detect ocp in the soft start circuit, hiccup operation start again. sw il 0 a ocp level 1 ms wait 1 ms wait ss pgood ocp detect note: pgood pin is connected v5_out through resistor. thermal s hutdown (tsd) thermal sensor monitors junction temperature of ic. when junction temperature exceeds 150 c, switching stops. after junction temperature become 1 35 c, ic restart switching from soft start (non - latched function). enhanced light load f unction (ell) ic operates diode emulation mode in light load condition. to enhance light load efficiency, ic detects light load condition automatically, and operate as enhanced light l oad mode (ell). in ell mode, bias current of ic becomes small, so this function can improve the efficiency. raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 13 of 23 aug 02, 2013 start - up sequence for external 5 v use when ldo function is used, start - up sequence is free. however, it needs specific start - up sequence when ldo function is not used. please set start - up sequence from following. ic cannot start - up when "v5_out & on/off rise first, vin rises secondly" sequence. (1) vin to v 5_out (on/off is pulled up to v 5_out ) vin v5_out (on/off) vout 4.3 v soft start period (2) vin or v 5_out to on/off (on/off = "h" asserted after vin & v 5_out rise) vin (or v5_out) v5_out (or vin) vout on/off note: vin, v5_out sequence does not matter in this start-up. soft start period on/off pin slew rate restriction when on/off pin is driven by another controller, the slew rate of h to l tr ansition must be higher than ? 5 v/ m s monotonically (must be rapid transition). if the slew rate is lower than ? 5 v/ m s (slow transition), switching noise affect on/off pin input circuit and lead to malfunction in case of heavy load state. recommended drive impedance of on/off pin is less than 10 k w . if on/off pin is always pulled up to v 5_out or vin via resistance, slew rate is not a matter. slew rate restriction: on/off is controlled externally no slew rate restriction: on/off is connected via resistance on/off v5_out 5v more than ?5v/ ms on/off v5_out 5v raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 14 of 23 aug 02, 2013 controller power supply the raa207703gbm incorporates intern al 5 v ldo, so it can operate with single power supply. ldo_en# can control ldo operation, and select the controller power supply from ldo or v5_ out pin. when ldo_en# = h state, external 5 v should be applied to v5_ out pin and avin pin. typical pin connect ion of each operation are below. operation with single power supply operation with multi power supply ldo_en# v5_out vin avin 5 v vin ldo_en# v5_out avin vin vin note: truth table for ldo_en# pin ldo_en# input 5 v regulator status "l" ldo enable "open" ldo enable "h" ldo disable stability criteria, output voltage settin g for high esr output capacitor small output ripple voltage makes control loop unstable in constant on time architecture. ripple voltage needs to be larger than 15 mv on fb pin. when using high esr (>50 m w ) capacitor such as electrolytic capacitor, polymer aluminum capacitor for output capacitor, ripple voltage on fb pin will be more than 15 mv. sw fb vout r1 r2 cout lout vin esr stability criteria from loop stability analysis, constant on time control system must satisfy below equat ion. stability criteria: esr ? cout > ton / 2 ? (6) here, ton is constant on time. if the system cannot satisfy above equation, subharmonic oscillation will occur. vout setting fb comparator compares fb voltage and internal accurate reference voltage (0.8 v). feedback loop controls fb voltage to match the reference voltage. however, vout ripple voltage affects fb voltage. so, effective fb pin voltage vfb will be below. (here, vout ripple from bulk capacitance is ignored) effective fb voltage (vfb): 0.8 v + ? ((vin ? vout) ? ton ? esr ? r2 / (lout ? (r1 + r2))) [v] ? (7) here, r1 and r2 is output voltage divider resist o r, lout is inductance of output filter and esr means esr of output capacitor (refer to above figure). 0.8 v in above equation means reference v oltage of ic. considering vout ripple voltage, vout voltage becomes below equation. vout: v fb ? (r1 + r2) / r2 [v] ? (8) raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 15 of 23 aug 02, 2013 operating with small esr output capacitor when using low - esr output capacitor like mlcc, voltage ripple on output voltage node is very small. so , voltage ripple needs to be enhanced by additional components. recommended ripple enhance method is like below figure. vout rf cf cr sw fb vin lout r1 r2 esr(<5m w) cout ripple injection on fb pin rf and cf make ripple voltage using induc tor dcr ripple. cr is used for ac ripple injection to fb pin. ripple voltage between rf and cf is described by following equation. vripple: (vin ? v out ) ? ton / (rf ? cf) [ v ] ? ( 9 ) rf : (vin ? v out) ? ton / ( vripple ? cf) [v] ? (10) recommended ripple voltage is between 15 mv and 20 mv. stability criteria to keep voltage ripple amplitude on fb pin, below equation should be satisfied. stability criteria (1) : 1 / (2 p ? c f ? fsw) << 1 / (2 p ? c r ? fsw) << r1 ? r2 / (r 1 + r2 ) ? (11) here, fsw means switching freque ncy at ccm mode. recommended value for cf = 0.01 m f, and cr = 1000 pf. r1 and r2 are recommended between 10 k w and 100 k w . from loop stability analysis of above circuit configuration, the system must satisfy below equation. stability criteria (2) : lout ? c o ut / (rf ? cf) > ton / 2 ? (12) if the system cannot satisfy above equation, subharmonic oscillation will occur. capacitance - voltage dependence is must be considered when mlcc use. vout setting additional ripple voltage and esr voltage ripple also affect s vout accuracy. from above figure, total ripple voltage on fb pin is described by below equation. ripple voltage on fb pin: (vin ? vout) ? ton / (rf ? cf) + (vin ? vout) ? ton ? esr / (lout) [v] ? (13) effective fb pin voltage is described by below equatio n. effective fb voltage (vfb): 0.8 v + ? ((vin ? vout) ? ton / (rf ? cf) + (vin ? vout) ? ton ? esr / (lout)) [v] ? (14) so, actual vout voltage is described by below equation. vout: vfb ? (r1 + r2) / r2 [v] ? (15) raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 16 of 23 aug 02, 2013 boot resistance sw boot rboot 0.1 m /25v sw node spike occurs when ic is operating. turn - on spike voltage exceeds absolute maximum voltage of sw pin depends on operating condition. to suppress the spike voltage, adding boot resist o r (rboot) is effective. recommended rboot is below. part no. recommended rboot vin = 12 v vin = 5 v raa20770 3 gbm 3.9 w 0 w raa20770 4 gbm 2.0 w 0 w raa20770 5 gbm 0 w 0 w raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 17 of 23 aug 02, 2013 design example (vin = 12 v, vout = 1.2 v, fsw = 500 khz (at ccm), l = 0.47 m h) vout u7 raa207703gbm v5_out a1 sgnd a2 fb a3 ldo_en# a4 avin a5 vin_c2 c2 vin_c3 c3 vin_c4 c4 vin_c5 c5 vin_d5 d5 ss b4 on/off b5 boot b1 set b2 pgood b3 sw_d1 d1 sw_d2 d2 sw_d3 d3 sw_d4 d4 sw_c1 c1 sw_e1 e1 sw_f1 f1 sw_f2 f2 sw_f3 f3 sw_g1 g1 pgnd_e2 e2 pgnd_e3 e3 pgnd_e4 e4 pgnd_e5 e5 pgnd_f4 f4 pgnd_f5 f5 pgnd_g2 g2 pgnd_g3 g3 pgnd_g4 g4 pgnd_g5 g5 +12v on/off c1 1 m /10v c101 10 m /16v c111 22 m /6.3v c112 22 m /6.3v c113 22 m /6.3v c114 22 m /6.3v c115 22 m /6.3v c102 10 m /16v c103 10 m /16v 0.01 m /25v c4 1000p/25v c5 3300p/10v c3 r3 51k 0.1 m /25v c2 r4 30k r5 3.9 r6 15k r1 13k r2 27k 0.47 m h l1 1. setting of ton (constant on time) in this condition, calculated on time is from equation (1), calculated ton: 1.2 v / 12 v ? (1 / 500 khz) = 200 ns from equation (3), calculated r4 = (1.2v / (12 v ? 500 khz) ? 60 ns) ? (12 v ? 2 v) / ( 50 pf ? 1 v) = 28 k w so choose r4 = 30 k w from e24 series. so, actual on pulse ton is decided by equation (2), constant on time: ((50 pf ? 1 v / (12 v ? 2 v)) ? 30 k w + 60 ns = 210 ns 2. setting of ripple injection resistance voltage ripple on fb pin nee ds to be more than 15 mv. here, c4 = 0.01 m f, c5 = 1000 pf and esr of output cap = 0.5 m w . to obtain 15 mv additional ripple on fb pin from r6, c4 and c5 network circuit, r6 is calculated by equation (10). calculated r 6: (12 v ? 1.2 v) ? 210 ns / (15 mv ? 0.01 m f) = 15.1 k w so choose r6 = 15 k w from e24 series and actual ripple voltage from injection circuit becomes 15.1 mv. so, total ripple voltage on fb pin is calculate by equation (13) , total ripple voltage: (12 v ? 1.2 v) ? 210 ns / (15 k w ? 0.01 m f) + (12 v ? 1.2 v) ? 210 ns / 0.47 m h ? 0.5 m w =17.5 mv 3. setting of output voltage resistor from above setting, eff ective fb voltage is from equation (15), effective fb voltage: 800 mv + 17.5 mv / 2 = 808.8 mv when r1 = 13 k w , r2 is decided from equation ( 15). r2 = 13 k w / ((1.2 v / 808.8 mv) ? 1) = 26. 8 k w so, choose r2 = 27 k w from e24 series. raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 18 of 23 aug 02, 2013 4. stability criteria confirmation for output capacitor, please confirm stability criteria. stability criteria from equation (11), 1 / ( 2 p ? 0.0 1 m f ? 500 khz) = 32 w << 1 / ( 2 p ? 1000 pf ? 500 khz) = 318 w << 13 k w ? 27 k w / (13 k w + 27 k w ) = 8.8 k w so, above criteria is satisfied. for output capacitor, please confirm stability criteria. stability criteria from equation (12), cout > (210 ns / 2) ? 1 5 k w ? 0.01 m f / 0.47 m h = 34 m f so, choose 110 m f (22 m f 5 pcs.) for output capacitor. here, please consider voltage dependence of capacitor. if you cannot satisfy above criteria, please consider below changes. ? increase l or cout value ? increase frequency (decrease c onstant on time) ? change rf value. 5. other components c1 = 1 m f / 10 v and c2 = 0.1 m f / 25 v are recommended. c3 decides soft start period from equation (5). r5 is decided from the table in ?boot r esistance? section. input and output capacitor s are decid ed considering voltage ripple, current ri pple and voltage tolerance. raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 19 of 23 aug 02, 2013 board layout example (raa20770 3 gbm) board layer example: 4 layer, internal 2nd and 3rd layer are used for gnd plane. sw plane sw plane gnd plane gnd plane vin plane t op layer bottom layer vin plane v out plane 1. power part ? input capacitor should be placed close to vin and pgnd pin to reduce switching noise and to improve the efficiency. ? many thermal via should be placed on vin, sw and pgnd planes to spread heat to board. furthermore, vin, sw planes on bottom layer are e ffective for thermal spread (if available). 2. control part ? decoupling capacitor between v 5_out and sgnd should be placed as close as possible to the chip in order to stable operation. ? also, sgnd, pgnd via should be placed as close as possible to the chip, a nd connect each pin low impedance by internal gnd plane. ? fb resistance should be placed close to chip and fb wiring should be short to avoid noise. furthermore, additional ripple circuit wiring should be kept away from high dv/dt plane such as sw and boot wirin g. ? to ensure the reliability of chip - board connection, we recommend solder mask defined (smd) layout. but you can also use non - solder mask defined (nsmd) layout as far as you can ensure the reliability. in the case of smd layout, we recommend below size. solder resist open size: 280 m m, land size: 280 m m + 50 to 100 m m (please consider processing accuracy) raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 20 of 23 aug 02, 2013 representative inductors maker inductance [ m h] d l/l0 = 20% change [a] dimensions [mm] nec tokin mpc series 0.42 20.0 6.7 8.0 4.0 0.60 19.0 6. 7 8.0 5.0 0.88 24.0 10.0 11.5 4.0 1.0 25.0 10.0 11.7 5.5 alps green device glmc series 0.47 13.9 * 1 6.5 7.4 3.0 1.0 10 * 1 6.5 7.4 3.0 1.5 8.8 * 1 6.5 7.4 3.0 toko fdve0630 series 0.33 15.9 6.7 7.4 3.0 0.47 15.6 6.7 7 .4 3.0 0.75 10.9 6.7 7.4 3.0 1.0 9.5 6.7 7.4 3.0 tdk spm5030 series 0.35 14.9 5.0 5.2 3.0 0.47 11.0 5.0 5.2 3.0 0.75 9.7 5.0 5.2 3.0 note: * 1 30% change small size inductor for raa20770 5 gbm maker inductance [ m h] d l/l0 = 3 0 % change [a] dimensions [mm] toko fdsd0420 series 0.68 8.3 4.2 4.2 2.0 1.0 6.8 4.2 4.2 2.0 1.5 5.7 4.2 4.2 2.0 tdk spm4012 series 0.47 8.3 4.4 4.1 1.2 1.0 4.8 4.4 4.1 1.2 representative output capacitors maker maximum voltage [v] capacitance [ m f ] sanyo poscap series 2.0 to 10 47 to 330 sanyo os - con series 2.0 to 10 47 to 330 murata mlcc series 6.3 to 10 22 to 47 tdk mlcc series 6.3 to 10 22 to 47 taiyo yuden mlcc series 6.3 to 10 22 to 47 raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 21 of 23 aug 02, 2013 package dimensions raa20770 3 g bm note: 1. ball pitch dimension is specified with the center of balls. 2. datum a and b are axes defined by the ball grid array, not by the package outline. unit: mm swbg0035za-a ? 0.02g ? mass[typ.] renesas code previous code jeita package code 0.05 2.67 0.05 35? ? 0.32 0.05 0.335 0.05 0.265 0.05 0.265 0.05 0.4 0.04 0.235 0.04 0.33 0.335 0.05 a b c d e f g 5 3 2 c area 1 4 3.87 0.05 4 c area seating plane 3.34 0.67 0.67 0.5 0.5 0.5 0.5 0.5 b 2.0 ? 0.05 m s ab s s 0.08 a raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 22 of 23 aug 02, 2013 raa20770 4 gbm unit: mm swbg0030za-a ? 0.02g ? mass[typ.] renesas code previous code jeita package code note: 1. ball pitch dimension is specified with the center of balls. 2. datum a and b are axes defined by the ball grid array, not by the package outline. 0.05 2.67 0.05 30? ?0.32 0.05 0.335 0.05 0.265 0.05 0.265 0.05 0.4 0.04 0.235 0.04 0.08 0.335 0.05 a b c d e f 5 3 2 c area 1 4 3.37 0.05 4 c area seating plane 2.84 0.67 0.67 0.5 0.5 0.5 0.5 b 2.0 ? 0.05 m s ab s s 0.08 a raa207703gbm/7704gbm/7705gbm r07ds0892ej0100 rev.1.00 page 23 of 23 aug 02, 2013 raa20770 5 gbm 0.05 2.67 0.05 20? ?0.32 0.05 0.335 0.05 0.265 0.05 0.265 0.05 0.4 0.04 0.235 0.04 0.25 0.335 0.05 a b c d 5 3 2 c area 1 4 2.37 0.05 4 c area seating plane 1.84 1.84 0.67 0.67 0.5 0.5 b 2.0 ? 0.05 m s ab s s 0.08 a note: 1. ball pitch dimension is specified with the center of balls. 2. datum a and b are axes defined by the ball grid array, not by the package outline. unit: mm swbg0020za-a ? 0.01g ? mass[typ.] renesas code previous code jeita package code ordering information part name quantity shipping container raa20770 3 gbm#hc0 2000 pcs taping reel raa20770 4 gbm#hc0 2000 pcs taping reel raa20770 5 gbm#hc0 2000 pcs taping reel notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 3. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". the recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. 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